View CY62126DV30LL-55ZI_4112160.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62126DV30 MoBL(R)
1-Mbit (64K x 16) Static RAM
Features
* Very high speed -- 55 ns * Temperature Ranges -- Industrial: -40C to 85C -- Automotive: -40C to 125C * Wide voltage range -- 2.2V - 3.6V * Pin compatible with CY62126BV * Ultra-low active power -- Typical active current: 0.85 mA @ f = 1 MHz -- Typical active current: 5 mA @ f = fMax (55 ns speed) * Ultra-low standby power * Easy memory expansion with CE and OE features * Automatic power-down when deselected * Available in Pb-free and non Pb-free 48-ball VFBGA and 44-pin TSOP Type II packages advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE CE OE BLE
A12
A11
A13
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05230 Rev. *H
*
198 Champion Court
A14 A15
*
San Jose, CA 95134-1709 * 408-943-2600 Revised July 18, 2006
[+] Feedback
CY62126DV30 MoBL(R)
Product Portfolio
Power Dissipation Operating, ICC (mA) VCC Range (V) Product CY62126DV30L CY62126DV30LL Range Automotive Industrial Min. 2.2 Typ. 3.0 Max. 3.6 Speed (ns) 55 55 f = 1 MHz Typ.[2] 0.85 0.85 Max. 1.5 1.5 f = fMax Typ.[2] 5 5 Max. 10 10 Standby, ISB2 (A) Typ.[2] 1.5 1.5 Max. 15 4
Pin Configurations[3, 4]
48-ball VFBGA Top View
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 NC 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
TSOP II (Forward) Top View
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
I/O12 DNU I/O13 NC A8 A14 A12 A9
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 3. NC pins are not connected to the die. 4. E3 (DNU) can be left as NC or VSS to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
Document #: 38-05230 Rev. *H
Page 2 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ..............................................................-0.3 to 3.9V DC Voltage Applied to Outputs in High-Z State[6] ....................................-0.3V to VCC + 0.3V DC Input Voltage[6] ................................ -0.3V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Industrial Automotive Ambient Temperature (TA) -40C to +85C -40C to +125C VCC[7] 2.2V to 3.6V 2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
CY62126DV30-55 Parameter VOH Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage 2.2V < VCC < 2.7V 2.7V < VCC < 3.6V 2.2V < VCC < 2.7V 2.7V < VCC < 3.6V 2.2V < VCC < 2.7V 2.7V < VCC < 3.6V Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA 1.8 2.2 -0.3 -0.3 Ind'l Auto GND < VO < VCC, Output Disabled Ind'l Auto f = fMax = 1/tRC f = 1 MHz VCC = 3.6V, IOUT = 0 mA, CMOS level L Ind'l Auto LL -1 -4 -1 -4 5 0.85 1.5 1.5 1.5 Min. 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +4 +1 +4 10 1.5 5 15 4 A A mA A A V V V Typ.[5] Max. Unit V
VOL
VIH
VIL
Input LOW Voltage 2.2V < VCC < 2.7V 2.7V < VCC < 3.6V
IIX
Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current-- CMOS Inputs
GND < VI < VCC
IOZ
ICC
ISB1
CE > VCC - 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fMax (Address and Data Only), f = 0 (OE, WE, BHE and BLE) CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V
ISB2
Automatic CE Power-down Current-- CMOS Inputs
L
Ind'l Auto
1.5 1.5 1.5
5 15 4
LL
Notes: 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 6. VIL(min.) = -2.0V for pulse durations less than 20 ns., VIH(max.) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device operation requires linear ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 s.
Document #: 38-05230 Rev. *H
Page 3 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 8 8 Unit pF pF
Thermal Resistance[8]
Parameter JA JC Description Test Conditions TSOP 55 12 VFBGA 76 11 Unit C/W C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch, 2-layer printed circuit board Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT THEVENIN EQUIVALENT RTH VTH R2
VCC Typ 10% GND Rise TIme: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns
Parameters R1 R2 RTH VTH
2.5V 16600 15400 8000 1.2
3.0V 1103 1554 645 1.75
Unit Ohms Ohms Ohms Volts
Data Retention Characteristics
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC=1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V L L LL tCDR[8] tR[9] Chip Deselect to Data Retention Time Operation Recovery Time Ind'l Auto Ind'l 0 100 Conditions Min. 1.5 4 10 3 ns s Typ[2] Max. Unit V A
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes: 8. Tested initially and after any design or proces changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 s.
Document #: 38-05230 Rev. *H
Page 4 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Switching Characteristics (Over the Operating Range)[10]
CY62126DV30-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[11, 12] 10 55 40 40 0 0 40 40 25 0 20 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[11] OE HIGH to High Z[11, 12] CE LOW to Low Z CE HIGH to High
[11]
Description
Min.
Max.
Unit
55 55 10 55 25 5 20 10 20 0 55 25 5 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Z[11, 12]
CE LOW to Power-up CE HIGH to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[11]
BLE/BHE HIGH to High-Z[11, 12]
WE HIGH to Low Z[11]
Notes: 10. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05230 Rev. *H
Page 5 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC CE tACE OE
tDOE
tPD tHZCE
tHZOE
BHE/BLE
ttLZOE LZOE
tHZBE
tDBE
tLZBE HIGH IMPEDANCE DATA OUT tLZCE tPU VCC SUPPLY CURRENT 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05230 Rev. *H
Page 6 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Switching Waveforms(continued)
Write Cycle No. 1 (WE Controlled[12, 13, 16, 17, 18]
tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)[12, 13, 16, 17, 18]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Notes: 17. Data I/O is high-impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05230 Rev. *H
Page 7 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Switching Waveforms(continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
tWC ADDRESS tSCE CE
BHE/BLE
tBW
tAW tSA WE tPWE
tHA
tSD DATAI/O NOTE 19 tHZWE DATAIN VALID
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE-controlled, OE LOW)[17, 18]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE tPWE tSD DATA I/O tHD tBW tHA
NOTE 19
DATAIN VALID
Document #: 38-05230 Rev. *H
Page 8 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Truth Table
CE H L L L L L L L L L L WE X X H H H L L L H H H OE X X L L L X X X H H H BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/O0-I/O15) High Z (I/O8-I/O15); Data Out (I/O0-I/O7) Data Out (I/O8-I/O15); High Z (I/O0-I/O7) Data In (I/O0-I/O15) High Z (I/O8-I/O15); Data In (I/O0-I/O7) Data in (I/O8-I/O15); High Z (I/O0-I/O7) High Z High Z High Z Mode Deselect/Power-Down Output Disabled Read Read Read Write Write Write Output Disabled Output Disabled Output Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62126DV30LL-55BVI CY62126DV30LL-55BVXI CY62126DV30LL-55ZI CY62126DV30LL-55ZXI CY62126DV30L-55BVXE CY62126DV30L-55ZSXE 51-85150 51-85087 51-85087 Package Diagram 51-85150 Package Type 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) (Pb-free) 44-pin TSOP II 44-pin TSOP II (Pb-free) 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) (Pb-free) 44-pin TSOP II (Pb-free) Automotive Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05230 Rev. *H
Page 9 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Package Diagrams
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
TOP VIEW
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
Document #: 38-05230 Rev. *H
Page 10 of 12
[+] Feedback
CY62126DV30 MoBL(R)
Package Diagrams(continued)
44-pin TSOP II (51-85087)
51-85087-*A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05230 Rev. *H
Page 11 of 12
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY62126DV30 MoBL(R)
Document History Page
Document Title: CY62126DV30 MoBL(R) 1-Mbit (64K x 16) Static RAM Document Number: 38-05230 REV. ** *A Orig. of ECN NO. Issue Date Change Description of Change 117689 127313 08/27/02 06/13/03 JUI MPR New Data Sheet Changed From Advanced Status to Preliminary. Changed ISB2 to 5 A (L), 4 A (LL) Changed ICCDR to 4 A (L), 3 A (LL) Changed CIN from 6 pF to 8 pF Changed from Preliminary to Final Add 70-ns speed, updated ordering information Changed ICC 1 MHz typ from 0.5 mA to 0.85 mA Fixed typo: Changed tDBE from 70 ns to 35 ns Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #8 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-pin TSOP-II package name from Z44 to ZS44 Added Temperature Ranges in the Features Section on Page # 1 Added Automotive Product Information for CY62126DV30-L for 55 ns Added ISB1 and ISB2 values for Automotive range of CY62126DV30-L for 55 ns Added Automotive Information for ICCDR in the Data Retention Characteristics table Added Pb-free packages in the ordering information Changed 44-pin TSOP-II package name from ZS44 to Z44 Added Pin Configuration and Package Diagram for 56-Lead QFN Package Updated Thermal Characteristics and Ordering Information Table Added Automotive Specs for IIX and IOZ in the DC Electrical Characteristics table on Page# 4 Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Removed 45 ns and 70ns Speed bin from Product offering Removed 56-pin QFN package Updated Ordering Information Table
*B *C *D *E
128340 129002 238050 316039
07/22/03 08/29/03 See ECN See ECN
JUI CDY AJU PCI
*F
335861
See ECN
SYT
*G
357256
See ECN
PCI
*H
486789
See ECN
VKN
Document #: 38-05230 Rev. *H
Page 12 of 12
[+] Feedback

▲Up To Search▲

Price & Availability of CY62126DV30LL-55ZI

	To Download CY62126DV30LL-55ZI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .